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1 ?2004 integrated device technology, inc. february 2004 dsc-5675/2 i/o control address decoder a 12l (1) a 0l memory array arbitration interrupt semaphore logic oe l r/ w l ce l 5675 drw 01 oe r r/ w r ce r sem l int l m/ s sem r int r (3) (3) 13 13 a 12r (1) a 0r address decoder i/o control busy l i/o 8l -i/o 15l i/o 0l -i/o 7l busy r i/o 8r -i/o 15r i/o 0r -i/o 7r (2,3) (2 ,3) , input read register and output drive register oe l r/ w l ce l oe r r/ w r ce r irr 0 ,irr 1 odr 0 - odr 4 r/ w l ub l lb l ce l oe l r/ w r ub r lb r ce r oe r sfen preliminary idt70p258/248l very low power 1.8v 8k/4k x 16 dual-port static ram features true dual-ported memory cells which allow simultaneous reads of the same memory location high-speed access ? industrial: 55ns (max.) low-power operation idt70p258/248l active: 27mw (typ.) standby: 3.6 w (typ.) separate upper-byte and lower-byte control for multiplexed bus compatibility idt70p258/248 easily expands data bus width to 32 bits or more using the master/slave select when cascading more than one device m/ s = v dd for busy output flag on master m/ s = v ss for busy input on slave input read register output drive register busy and interrupt flag on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port lvttl-compatible, single 1.8v (100mv) power supply available in 100 ball 0.5mm-pitch bga industrial temperature range (-40c to +85c) functional block diagram notes: 1. a 12 x is a nc for idt70p248. 2. (master): busy is output; (slave): busy is input. 3. busy outputs and int outputs are non-tri-stated push-pull. supports 3.0v and 1.8v i/o's
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 2 preliminary description the idt70p258/248 is a very low power 8k/4k x 16 dual-port static ram. the idt70p258/248 is designed to be used as a stand-alone 128/64k-bit dual-port sram or as a combination master/slave dual- port sram for 32-bit-or-more word systems. using the idt master/ slave dual-port sram approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 27mw of power. the idt70p258/248 is packaged in a 100 ball 0.5mm- pitch ball grid array. the package is a 1mm thick and designed to fit in wireless handset applications. pin configurations (2,3,4) c10 d8 c8 a9 d9 c9 b9 d10 c7 b8 a8 a10 d7 b7 a7 b6 c6 d6 a5 b5 c5 d5 a4 b4 c4 d4 a3 b3 c3 d3 d2 c2 b2 a2 a1 b1 c1 d1 e1 e2 e3 e4 f1 f2 f3 f4 g1 g2 g3 g4 h1 h2 h3 h4 j1 j2 j3 j4 k1 k2 k3 k4 a6 b10 e5 e6 e7 e8 e9 e10 f5 f6 f8 f9 f10 g5 g6 g7 g8 g9 g10 h5 h6 h7 h8 h9 h10 j5 j6 j7 j8 j9 j10 k5 k6 k7 k8 k9 k10 f7 5675 drw 02b , 09/04/03 a 5r a 8r a 11r ub r vss vss sem r i/o 15r i/o 12r i/o 10r vss vss a 6r i/o 7r i/o 11r i/o 14r a 2r a 1r a 0r lb r vss vss sfen vss vss v dd a 3r a 7r a 9r ce r r/ w r oe r i/o 9r i/o 6r a 4r v dd v dd a 12r (1) a 10r int r i/o 13r i/o 5r busy r i/o 2r odr 2 odr 4 i/o 8r m/ s odr 3 int l irr 1 i/o 4r i/o 1r odr 1 busy l a 1l nc nc oe l i/o 0r i/o 3r i/o 15l v ddql odr 0 a 2l a 5l a 12l (1) v dd i/o 3l i/o 11l i/o 12l i/o 14l i/o 13l a 0l a 4l a 9l lb l ce l i/o 1l v ddql i/o 10l a 3l a 7l a 10l irr 0 i/o 4l i/o 6l i/o 8l i/o 9l a 6l a 8l a 11l ub l sem l r/ w l i/o 0l i/o 2l i/o 5l i/o 7l vss 70p258/248by by-100 100-ball 0.5mm pitch bga top view (5) notes: 1. a 12 x is a nc for idt70p248. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. by100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking.
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 3 preliminary pin names left port right port names ce l ce r chip enable (input) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 12l (1) a 0r - a 12r (1) address (input) i/o 0l - i/o 15l i/o 0r - i/o 15r data input/output sem l sem r semaphore enable (input) ub l ub r upper byte select (input) lb l lb r lower byte select (input) int l int r interrupt flag (output) busy l busy r busy flag irr 0 , irr 1 input read register (input) odr 0 - odr 4 output drive register (output) sfen (2) special function enable (input) m/ s master or slave select (input) v dd power (1.8v) (inp ut) v ddql left port i/o supply voltage (3.0v) (input) v ss ground (0v) (input) 5675 tbl 01 note: 1. a 12 x is a nc for idt70p248. 2. sfen is active when either ce l = v il or ce r = v il . sfen is inactive when ce l = ce r = v ih . note: 1. a 0l ? a 12l a 0r ? a 12r truth table i: non-contention read/write control inputs (1) outputs mode ce r/ w oe ub lb sem i/o 8-15 i/o 0-7 h x x x x h high-z high-z deselected: power down x x x h h h high-z high-z both bytes deselected llxlhhdata in high-z write to upper byte only llxhlhhigh-zdata in write to lower byte only llxllhdata in data in write to both bytes lhllhhdata out high-z read upper byte only lhlhlhhigh-zdata out read lower byte only lhlllhdata out data out read both bytes x x h x x x high-z high-z outputs disabled 5675 tbl 02
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 4 preliminary truth table ii: semaphore read/write control (1) note: 1. there are eight semaphore flags written to via i/o 0 and read from all of the i/o's (i/o 0 -i/o 15 ). these eight semaphores are addressed by a 0 -a 2 . inputs outputs mode ce r/ w oe ub lb sem i/o 8-15 i/o 0-7 hhlxx ldata out data out read data in semaphore flag xhlhhldata out data out read data in semaphore flag h xxxldata in data in write d in0 into semaphore flag x xhhldata in data in write d in0 into semaphore flag lxxlxl ____ ____ not allowed lxxxll ____ ____ not allowed 5675 tbl 03 absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period over v term = v dd + 0.3v . 3. ambient temperature under dc bias. no ac conditions. chip deselected. 4. v ddqlmax + 0.3v for left port. symbol rating commercial & industrial unit v term (2) terminal voltage with respect to gnd -0.5 to v ddmax +0.3v (4) v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddql = 3.0v) dc output current 20 ma i out (for v ddql = 1.8v) dc output current 20 ma 5675 tbl 04
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 5 preliminary capacitance (ta = +25c, f = 1.0mhz) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 11 pf 5675 tbl 07 maximum operating temperature and supply voltage (1) notes: 1. this is the parameter t a . this is the "instant on" case temperature. grade ambient temperature gnd v dd industrial -40 o c to +85 o c0v1.8v + 100mv 5675 tbl 05 recommended dc operating conditions notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed v dd + 0.3v. 3. sfen operates at the 1.8v v i h and v il voltage levels. 4. m/ s operates at the v dd and v ss voltage levels. symbol parameter min. typ. max. unit v dd supply voltage (4) 1.7 1.8 1.9 v v ddql left port supply voltage 2.7 3.0 3.3 v v ss ground 0 0 0 v v ihl input high voltage (v ddql = 3.0v) 2.0 ___ v ddql + 0.2 v v ill input low voltage (v ddql = 3.0v) -0.2 ___ 0.6 v v ihr input high voltage (3) 1.2 ___ v dd + 0.2 v v ilr input low voltage (3) -0.2 ___ 0.4 v 5675 tbl 06
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 6 preliminary dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8v 100mv) notes: 1. v dd = 1.8v, t a = +25c, and are not production tested. i dd dc = 15ma ( typ .) 2. at f = f max , address and control lines are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions?. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. if m/ s = v ss , then f busyl = f busyr = 0 for full standby mode. 70p258/248 ind'l only symbol parameter test condition version typ. (1) max. unit i dd dynamic operating current (both po rts active ) ce = v il , outputs open f = f max (2) ind'l l 15 25 ma i sb1 standby current (both ports inactive ) ce r and ce l = v ih, sem r = sem l = v ih f = f max (2) ind'l l 2 8 a i sb2 standby current (one port inactive , one port active) ce " a " = v il and ce " b " = v ih (3) , active port outputs open f = f max (2) ind'l l 8.5 14 ma i sb3 full standby current (both ports inactive - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, sem l and sem r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v m/ s = v dd or v ss (4) , f = 0 ind'l l 2 8 a i sb4 standby current (one port inactive , one port active - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (4) v in > v dd - 0.2v or v in < 0.2v, active port outputs open f = f max (2) ind'l l 8.5 14 ma 5675 tbl 09 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8v 100mv) symbol parameter test conditions min. max. unit i li input leakage current v dd = 1.8v, v in = 0v to v dd ___ 1 a i lo output leakage current ce = v ih , v out = 0v to v dd ___ 1 a v oll output low voltage (v ddql = 3.0v) i oll = +2ma ___ 0.4 v v ohl output high voltage (v ddql = 3.0v) i ohl = -2ma 2.1 ___ v v olr output low voltage i olr = +0.1ma ___ 0.2 v v ohr output high voltage i ohr = -0.1ma v dd - 0.2v ___ v 5675 tbl 08
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 7 preliminary r1 r2 30pf (1) 3.0v / 1.8v 5675 drw 03 figure 1. ac output test load (5pf for t lz , t hz , t wz , t ow ) 3.0v 1.8v r1 1022 ? 13500 ? r2 729 ? 10800 ? 5675 tbl 10_5 timing of power-up power-down 5675 drw 04 t pu i cc i sb t pd ce 50% 50 % , ac test conditions input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v/gnd to 1.8v 3ns max. 1.5v/0.9v 1.5v/0.9v figure 1 5675 tbl 10
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 8 preliminary ac electrical characteristics over the operating temperature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load. 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il , ub or lb = v il , and sem = v ih. to access semaphore, ce = v ih or ub and lb = v ih , and sem = v il . 4. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. at any given temperature and voltage condition, t hz is less than t lz for any given device. 70p258/248 ind'l only unit symbol parameter min. max. read cycle t rc read cycle time 55 ____ ns t aa address access time ____ 55 ns t ace chip enable access time (3) ____ 55 ns t abe byte enable access time (3) ____ 55 ns t aoe output enable access time (3) ____ 30 ns t oh output hold from address change 5 ____ ns t lz output low-z time (1,2,5) 5 ____ ns t hz output high-z time (1,2,5) ____ 25 ns t pu chip enable to power up time (1,2) 0 ____ ns t pd chip disab le to power do wn time (1,2) ____ 55 ns t sop semaphore flag update pulse ( oe or sem )15 ____ ns t saa semaphore address access (3) ____ 55 ns 5675 tbl 11
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 9 preliminary t rc r/ w ce addr t aa oe ub , lb 5675 drw 05 (4) t ace (4) t aoe (4) t abe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) , waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last, oe , ce , lb , or ub . 2. timing depends on which signal is de-asserted first ce , oe , lb , or ub . 3. t bdd delay is required only in cases where opposite port is completing a write operation to the same address location. for simultane ous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t abe , t aoe , t ace , t aa or t bdd . 5. sem = v ih .
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 10 preliminary notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load. 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access sram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih or ub and lb = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . ac electrical characteristics over the operating temperature and supply voltage (4) symbol parameter 70p258/248 ind'l only unit min. max. write cycle t wc write cycle time 55 ____ ns t ew chip enable to end-of-write (3) 45 ____ ns t aw address valid to end-of-write 45 ____ ns t as address set-up time (3) 0 ____ ns t wp write pulse width 40 ____ ns t wr write recovery time 0 ____ ns t dw data valid to end-of-write 30 ____ ns t hz output high-z time (1,2) ____ 25 ns t dh data hold time (4) 0 ____ ns t wz write enable to output in high-z (1,2) ____ 25 ns t ow output active from end-of-write (1,2,4) 0 ____ ns t swrd sem flag write to read time 10 ____ ns t sps sem flag contention window 10 ____ ns 5675 tb l 12
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 11 preliminary timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) notes: 1. r/ w or ce or ub & lb must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ub or lb and a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w going high (or sem going low) to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce , r/ w or byte control. 7. this parameter is guaranteed by device characterization, but is not production tested.transition is measured 0mv from low or high-impedance voltage with output test load. 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access sram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih or ub and lb = v ih and sem = v il . either condition must be valid for the entire t ew time. r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) 5675 drw 06 ce or sem (7) (3) , ce or sem (9) (9) (9) address t aw ce or sem t wc 5675 drw 07 t as t wr t dw t dh data in r/ w t ew ub or lb (9) (3) (2) (6) ,, timing waveform of write cycle no. 2, ce , ub , lb controlled timing (1,5)
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 12 preliminary timing waveform of semaphore read after write timing, either side (1) timing waveform of semaphore write contention (1,3,4) notes: 1. d 0r = d 0l = v il , ce r = ce l = v ih , or both ub & lb = v ih . 2. all timing is the same for left or right port. ?a? may be either left or right port. ?b? is the opposite port from ?a?. 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied there is no guarantee which side will be granted the semaphore flag. notes: 1. ce = v ih or ub & lb = v ih for the duration of the above timing (both write and read cycle). 2. ?data out valid? represents all i/o's (i/o 0 -i/o 15 )equal to the semaphore value. sem "a" 5675 drw 09 t sps match r/w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/w "b" a 0"b" -a 2"b" side (2) "b" sem t ew 5675 drw 08 t aw i/o 0 valid address t saa r/ w t wr t o h t ace valid address data in valid t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe data out valid (2) , t sop
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 13 preliminary ac electrical characteristics over the operating temperature and supply voltage range notes: 1. port-to-port delay through sram cells from writing port to reading port, refer to "timing waveform of read with busy (m/ s = v dd )" or "timing waveform of write with port-to-port delay (m/ s = v ss )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0ns, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited during contention. 5. to ensure that a write cycle is completed after contention. 70p258/248 ind'l only symbol parameter min. max. unit busy timing (m/ s = v dd ) t baa busy access time from address match ____ 45 ns t bda busy disable time from address not matched ____ 45 ns t bac busy access time from chip enable low ____ 45 ns t bdc busy disab le time from chip enable high ____ 45 ns t aps arbitration priority set-up time (2) 5 ____ ns t bdd busy disable to valid data (3) ____ 40 ns t wh write hold after busy (5) 35 ____ ns busy timing (m/ s = v ss ) t wb busy input to write (4) 0 ____ ns t wh write hold after busy (5) 35 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 80 ns t ddd write data valid to read data delay (1) ____ 65 ns 5675 tb l 13
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 14 preliminary timing waveform of slave write (m/ s = v il ) 5675 drw 11 r/ w "a" busy "b" t wp t wb (3) r/ w "b" t wh (1) (2) , notes : 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the ?slave? version. 5675 drw 10 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa , timing waveform of read with busy (2,4,5) (m/ s = v ih ) notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il . 3. oe = v il for the reading port. 4. if m/ s = v ss (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for both left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a".
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 15 preliminary waveform of busy arbitration controlled by ce timing (1) (m/ s = v ih ) waveform of busy arbitration cycle controlled by address match timing (1) (m/ s = v ih ) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 5675 drw 12 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) , 5675 drw 13 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" , ac electrical characteristics over the operating temperature and supply voltage range 70p258/248 ind'l only symbol parameter min. max. unit interrupt timing t as address set-up time 0 ____ ns t wr write recovery time 0 ____ ns t ins interrupt set time ____ 45 ns t inr interrupt reset time ____ 45 ns 5675 tb l 14
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 16 preliminary waveform of interrupt timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. see interrupt truth table iii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. 5675 drw 14 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) , 5675 drw 15 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2) ,
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 17 preliminary truth table iii ? interrupt flag (1) notes: 1. assumes busy l = busy r = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. a 12 x is a nc for idt70p248, therefore interrrupt addresses are fff and ffe. left port right port function r/ w l ce l oe l a 12l -a 0l (4) int l r/ w r ce r oe r a 12r -a 0r (4) int r llx1fffxxxx x l (2) se t right int r flag xxxxxxll1fff h (3) re set right int r flag xxx x l (3) l l x 1ffe x se t left int l flag x l l 1ffe h (2) x x x x x re set le ft int l flag 5675 tbl 15 truth table iv ? address busy arbitration notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt70p258/248 are push pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. l if the inputs to the opposite port were stable prior to the address and enable inputs of this port. v ih if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs cannot be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. inputs outputs function ce l ce r a 0l -a 12l a 0r -a 12r busy l (1) busy r (1) x x no match h h normal hx match h h normal xh match h h normal l l match (2) (2) write inhibit (3) 5675 tbl 16
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 18 preliminary truth table v ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70p258/248. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 15 ). these eight semaphores are addressed by a 0 -a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. functions d 0 - d 15 left d 0 - d 15 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5675 tbl 17 sfen ce r/ w oe ub lb addr i/o 0 -i/o 1 i/o 2 -i/o 15 mode hlhl l (1) l (1) x0000 - max valid (1) valid (1) standard memory access llhl x lx0000valid (2) x irr read (3) 5675 tbl 18 truth table vi ? input read register operation (3) notes: 1. ub or lb = v il . if lb = v il , then i/o 0 - i/o 7 are valid. if ub = v il , then i/o 8 - i/o 15 are valid. 2. lb must be active ( lb = v il ) for these bits to be valid. 3. sfen = v il to activate irr reads. sfen ce r/ w oe ub lb addr i/o 0 -i/o 4 i/o 5 -i/o 15 mode hlhx (1) l (2) l (2) x0000 - max valid (2) valid (2) standard memory access l l l x x l x0001 valid (3) x odr write (4,5) l l h l x l x0001 valid (3) x odr read (5) 5675 tbl 19 truth table vii ? output drive register operation (5) notes: 1. output enable must be low (oe = vil) during reads for valid data to be output. 2. ub or lb = v il . if lb = v il , then i/o 0 - i/o 7 are valid. if ub = v il , then i/o 8 - i/o 15 are valid. 3. lb must be active ( lb = v il ) for these bits to be valid. 4. during odr writes data will also be written to the memory. 5. sfen = v il to activate odr reads and writes.
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 19 preliminary device 1 device 2 irr 0 irr 1 input read register (address x0000) address & i/o control a 0l - a 12l a 0r - a 12r i/o 0l - i/o 15l i/o 0r - i/o 15r memory array 5675 drw 16 figure 3. input read register device 2 device 4 output drive register (address x0001) address & i/o control a 0l - a 12l a 0r - a 12r i/o 0l - i/o 15l i/o 0r - i/o 15r memory array 5675 drw 17 odr 0 odr 1 odr 2 odr 3 odr 4 device 1 device 3 device 5 figure 4. output drive register
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 20 preliminary figure 3. busy and chip enable routing for both width and depth expansion with idt70p258/248 srams. the busy outputs on the idt 70p258/248 sram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these srams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70p258/248 sram array in width while using busy logic, one master part is used to decide which side of the sram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt70p258/248 sram the busy pin is an output if the part is used as a master (m/ s pin = v dd ), and the busy pin is an input if the part used as a slave (m/ s pin = v ss ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. the input read register (irr) of the idt70p258/248 captures the status of two external binary input devices connected to the input read pins (e.g. dip switches). the contents of the irr are read as a standard memory access to address x0000 from either port and the data is output via the standard i/os (truth table vi). during input register reads i/o 0 - i/o 1 are valid bits and i/o 2 - i/o 15 are "dont' care". writes to address x0000 are not allowed from either port. when sfen = v il , the irr is active and address x0000 is not available for standard memory operations. when sfen = v ih , the irr is inactive and address x0000 can be used as part of the main memory. the irr supports inputs up to 3.5v (v il < 0.4v, v ih > 1.4v). refer to figure 3 and truth table vi for input read register operation. functional description the idt70p258/248 provides two ports with separate control, ad- dress and i/o pins that permit independent access to any location in memory. the idt70p258/248 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 1ffe (hex) (ffe for idt70p248), where a write is defined as the ce =r/ w =v il per truth table iii. the left port clears the interrupt by accessing address location 1ffe when ce r = oe r = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 1fff (hex) (fff for idt70p248) and to clear the interrupt flag ( int r ), the right port must read the memory location 1fff. the message (16 bits) at 1ffe or 1fff is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 1ffe and 1fff are not used as mail boxes, but as part of the random access memory. refer to truth table iiii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the sram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the sram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attemp-ted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. 5675 drw 18 master dual port sram busy l busy r ce master dual port sram busy l busy r ce slave dual port sram busy l busy r ce slave dual port sram busy l busy r ce busy l busy r d e c o d e r , input read register
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 21 preliminary the output drive register (odr) of the idt70p258/248 determines the state of up to five external binary-state devices by providing a path to v ss for the external circuit. the five external devices supported by the odr can operate at different voltages (1.5v < v supply < 3.5v), but the combined current of the devices must not exceed 40 ma (8ma i max for each external device). the status of the odr bits is set using standard write accesses from either port to address x0001with a ?1? corresponding to ?on? and a ?0? corresponding to ?off?. the status of the odr bits can also be read (without changing the status of the bits) via a standard read to address x0001. when sfen = v il , the odr is active and address x0001 is not available for standard memory operations. when sfen = v ih , the odr is inactive and address x0001 can be used as part of the main memory. during reads and writes to the odr i/o 0 - i/o 4 are valid bits and i/o 5 - i/o 15 are "don't care". refer to figure 4 and truth table vii for output drive register operation. semaphores the idt70p258/248 is an extremely fast dual-port 8k/4k x 16 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port sram to claim a privilege over the other processor for functions defined by the system designer?s software. as an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port sram or any other shared resource. the dual-port sram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be accessed to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non- semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port sram. these devices have an automatic power-down feature controlled by ce , the dual-port sram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table i where ce and sem are low. systems which can best use the idt70p258/248 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70p258/248's hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70p258/248 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are independent of the dual-port sram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active high. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70p258/248 in a separate memory space from the dual-port sram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side?s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the output drive register
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 22 preliminary subsequent read (see truth table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side?s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side?s request latch. the second side?s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. using semaphores?some examples perhaps the simplest application of semaphores is their application as resource markers for the idt70p258/248?s dual-port sram. say the 8k/ 4k x 16 sram was to be divided into two 4k/2k x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indicator for the upper section of memory. to take a resource, in this example the lower 4k/2k of dual-port sram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4k/2k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 4k/2k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 4k/2k blocks of dual-port sram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual-port sram or other shared resources into eight parts. sema- phores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was ?off-limits? to the cpu, both the cpu and the i/o devices could access their assigned portions of memory continu- ously without any wait states. semaphores are also useful in applications where no memory ?wait? state is available on one or both sides. once a semaphore handshake has been performed, both processors can access their assigned sram segments at full speed. another application is in the area of complex data structures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaran- teeing a consistent data structure. d 5675 drw 19 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read , figure 4. idt70p258/248 semaphore logic
6.42 idt70p258/248l low power 1.8v 8k/4k x 16 dual-port static ram industrial temperature range 23 preliminary ordering information 5675 drw 20 a power 999 speed a package a process/ temperature range i industrial (-40 cto+85 c) by 100 ball 0.5mm-pitch bga(by100) 55 llowpower xxxxx device type 128k (8k x 16) 1.8v dual-port sram 64k (4k x 16) 1.8v dual-port sram 70p258 70p248 idt speed in nanoseconds industrial only corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. preliminary datasheet: definition "preliminary' datasheets contain descriptions for products that are in early release. datasheet document history 09/11/03: initial datasheet 01/22/04: page 6 amended parameter and test conditions in dc electrical characteristics table

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